A dynamic power programmable 10-bit 20-MS/s pipeline ADC for ISM band wireless communication

This paper presents a 10-bit 20MS/s pipeline analog-to-digital converter implemented in 0.18 μ m CMOS technology with dynamic programmable power consumption. The proposed pipeline ADC achieves a typical performance of 58.47dB SNDR and 61.48dB SFDR with a minimum power dissipation of 5mW. Circuit techniques such as dynamic comparators, stage capacitor scaling and a novel dynamic programmable power switcher have been used to achieve this level of power consumption.