Design of Sample-Hold Circuit with SFDR Over 90 dB for High Speed ADC

This paper describes a sample-hold (SH) circuit for the front-ended pipelined 12-bit analog-to-digital converter (ADC). A differential OTA (operational transconductance amplifier) used in the sample-hold (SH) circuit is presented. The OTA is optimized for high-speed high-accuracy applications by using gain-boosted topology. By means of clamp circuit, the slewing rate of the OTA is greatly improved. The design uses the chartered 0.35-μm 2P4M CMOS process with a 3 V supply. The open-loop DC gain is over 110 dB and unity-gain bandwidth is 524.6 MHz. The slewing rate of the OTA is 1160 V/μs while the total load capacitance is 6pf. The SH circuit can settle within 10 ns to an accuracy of <0.01% for the worst case. The SH circuit achieves SFDR of 90.64 dB and THD −89.63 dB with sampling frequency 50 MHz. Design analysis and simulations are presented demonstrating that the amplifier exceeds the specification in the SH stage of a 12-bit pipelined ADC, while dissipating an average of 23 mW of power.