An On-chip Memory-Path Architecture on Merged DRAM/Logic LSIs for High-Performance/Log-Energy Consumption

Integrating a main memory (DRAM) and processors into a single chip, or a merged DRAM/logic LSI, makes available high on-chip memory bandwidth provided by widening on-chip bus and on-chip DRAM array. This approach is well known as a good solution to break the memory wall problem. For merged DRAM/logic LSIs having cache memory, we can exploit the high on-chip memory bandwidth by replacing a whole cache line at a time. This approach tends to increase the cache-line size if we attempt to exploit the attainable high on-chip memory bandwidth. A large cache-line size can give a benefit of prefetching effect if programs have rich spatial locality. However, it will bring the following disadvantages with poor spatial locality: