Subthreshold leakage power reduction in VLSI circuits: A survey

As technology enters into deep submicron regime, subthreshold leakage power increases exponentially and become a limiting factor in the performance of portable and battery operated electronic devices. To increase the life of battery and computational capacities of portable devices the reduction of power in standby/ sleep mode is evident. Now a day's power dissipation emerged as a major design constraint in the device miniaturization and integration of huge number of transistors. A detailed survey of alternative techniques to reduce subthreshold leakage power is presented in this paper.