A 2.0Vpp input, 0.5V supply Delta Amplifier with A-to-D conversion

Recent progress in scaled CMOS technologies can enhance a signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, inevitable supply voltage reduction causes signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To solve the problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP operates by folding an analog signal within a voltage window using a virtual ground amplifier, modulation switches and comparators. The folded delta signal has to be reconstructed to the ordinal signal. A reconstruction circuit is also proposed based on Analog-Time-Digital conversion (ATD) in which-pulse width analog information obtained at the comparators in DeltAMP, is converted to a digital signal by counting. A test chip of DeltAMP with ATD using a 90 nm CMOS technology, achieved input voltage range of 2.0 Vpp at a 0.5 V supply, and SNR of 62 dB at signal bandwidth of 120 kHz. Measured power consumption was as low as 150 muW at 0.5 V supply.