A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on

A fast power-on low-power signaling system was developed and fabricated in TSMC's 40nm LP process. The system uses matched source-synchronous clocking (MSSC), fast power-on bias, a rapid turn-on 4× multiplying ILO, and CML clock distribution to achieve 2.5-5.6Gb/s/lane and 8ns turn on at 2.4mW/Gb/s per link across a 6-lane parallel interface. First-edge clock jitter is minimized by using matching equalizers in the clock and data paths. PSN is reduced by using a staggered bias turn-on.