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Interconnect Design Strategy for High-Speed Logic LSIs
Interconnect Design Strategy for High-Speed Logic LSIs
1999
Masakazu Yamashina
Masayuki Mizuno
Atsufumi Shibayama
Keywords:
Logic synthesis
Electronic engineering
Logic family
Chip
Transmission line
Interconnection
Engineering
Design strategy
Electrical engineering
cmos logic circuits
Correction
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