A low-power 33 pJ/conversion-step 12-bit SAR resistance-to-digital converter for microsensors

In this paper, a low-power 12-bit successive approximation register (SAR) resistance-to-digital converter (RDC) for resistive microsensors with a figure-of-merit (FoM) of 33 pJ/conversion-step is presented. In the conventional resistive analog front-end (AFE), two-step conversion schemes, including a resistance-to-voltage converter and a voltage-to-digital converter are generally used. The presented SAR RDC can directly convert the resistance changes to digital codes. The proposed SAR RDC consists of a comparing stage, and a SAR operating stage. The preamplifier of comparing stage implements a correlated double sampling (CDS) technique to improve the low-noise characteristic and reduce the low-frequency flicker (1/f) noise. The RDC is designed using SAR scheme to achieve low-power consumption. The SAR RDC achieves a wide input resistance range of 2 MΩ. The SAR RDC is implemented with a 0.18 μm standard complementary metal–oxide–semiconductor (CMOS) process with an active area of 0.35 mm2. All functional blocks, including voltage and current references, oscillators, and timing generators, are integrated on the chip. The proposed RDC consumes 93.2 μW with 1.8 V power supply. The experimental results of the proposed SAR RDC achieve 11.3-bit resolution within a conversion time of 0.92 ms and a figure-of-merit (FoM) of 33 pJ/conversion-step.