Comparitive analysis of null convention logic and synchronous CMOS ripple carry adders

Null Conventional Logic (NCL) is one of the most robust design techniques amongst the other asynchronous design methodologies. The NCL circuits which follow Dual-rail logic are built from a library of 27 Threshold gates which are implemented using semi-static implementation. In this paper 1-bit, 4-bit and 8-bit NCL Ripple Carry Adders have been designed and compared with the corresponding Ripple Carry Adders implemented using conventional Synchronous CMOS level design methodologies. Comparisons are made in terms of power consumption, delay and transistor count. Results indicate that NCL circuits have a significant decrement in power consumption and lesser transistor count when compared to CMOS design. On an average NCL Full Adder circuits consume approximately 65% lesser power than their synchronous counterparts. All these designs are implemented on Cadence Virtuoso using 180nm technology.