Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis.

In modern day FinFET-based microprocessors, dynamic power consumes ~80% of chip power under high utilization conditions. These microprocessors cater to a broad range of workloads, each with its own unique power signature. In addition to the heterogeneity across the workloads, there is notable heterogeneity in power consumption profile across the chip, including within IP blocks. With increasing focus on reducing the time to market, new methods for efficient generation of accurate power abstracts of IP blocks, while capturing the heterogeneous signatures, are key for enabling rapid hierarchical chip power analysis. We present approaches to generate per clock gating domain parameterized power abstracts and evaluate it on real industry class high performance microprocessor designs. Experimental results demonstrate the accuracy and efficiency of the proposed approach when compared with direct gate level simulation based power estimation and existing IP power abstraction techniques.