Design Flow for a Reconfigurable Processor Implementation of a Turbo-decoder

2005 
This paper describes an approach to hardware/software design space exploration for reconfigurable processors. The existing compiler tool-chain, because of the user-definable instructions, needs to be extended in order to offer developers an easy way to explore the design space. Such extension often is not easy to use for developers who have only a software background, and are not familiar with reconfigurable architecture details or hardware design. Our approach differs from others because it is based on a simple extension of the standard programming model well known to software developers. We illustrate it by using a real case study, a software implementation of a UMTS turbo-decoder that achieves a 11× speed-up of the whole application, by exploiting user-defined instructions on the dynamically reconfigurable portion of the datapath.
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