Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing

Semiconductor manufacturing processes are very long and complex, needing several hundreds of individual steps to produce the final product (chip). In this context, the early detection of process excursions or product defects is very important to avoid massive potential losses. Metrology is thus a key step in the fabrication line. Whereas a 100 % inspection rate would be ideal in theory, the cost of the metrology devices and cycle time losses due to these measurements would completely inhibit such an approach. On another hand, the skipping of some measurements is risky for quality assurance and processing machine reliability. The purpose is to define an optimized quality control plan that reduces the required capacity of control while maintaining enough trust in quality controls. The method adopted by this research is to employ a multi-objective genetic algorithm to define the optimized control plan able to reduce the used metrology capacity without increasing risk level. Early results based on one month of real historical data computation reveal a possible reallocation of controls with a decrease by more than 15 % of metrology capacity while also reducing the risk level on the processing machine (expressed by the wafer at risk ($$W\[email protected]\[email protected])) by 30 %.