16.6 A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fs rms Jitter and-70dBc Fractional Spurs

To deliver a good EVM performance, modern communication standards, such as WiFi 802.11ax with a 1024-QAM mode, require RF clocks with extremely low integrated phase error and low spurs. Because of their good scalability, digital phase-locked loops (DPLLs) have been widely studied [1]–[3]. However, they face two problems: nonlinearity and quantization noise of time-to-digital converters (TDCs). High-performance DPLLs require complicated TDC structures and calibrations. By contrast, a bang-bang phase detector (PD), i.e., a one-bit TDC, can be linear and low noise [4]. However, in the fractional mode, the PD gain is lowered by the significant phase fluctuations from the fractional divider. The gain can be restored by calibration, but the nonlinearity of the calibration circuit creates large spurs in an otherwise good integrated rms noise [5]. A sub-sampling PLL [6] avoids amplifying the PD noise and eliminates the loop divider, but still needs calibration for fractional operation. This work describes a calibration-free fractional BBDPLL. With the assistance of two auxiliary PLLs, this triple-loop PLL architecture combines the advantages of the sub-sampling PLL and bang-bang PD to achieve $131fs_{\mathrm{rms}}$ jitter and lower than-70dBc fractional spurs.