Bit-level systolic carry-save array division

A bit-level systolic carry-save division array that allows bit-level pipelining, just as for carry-save array multipliers, is presented. This architecture leads to very fast, efficient and regular division implementations as needed in digital signal processing (DSP) applications such as speech processing or cryptography. The architecture is very well suited for integer division as well as for the division of normalized fixed-point mantissas used in floating-point number system implementations. >