1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar

We propose the architecture and manufacturing process of 6 surrounding-gate-transistor (SGT) SRAM cell for the 1.5nm technology node. The staggered layout and self-aligned patternings have successfully realized a transition from 5nm to 1.5nm node with the same SGT diameter. Electrical characteristics by TCAD simulation are finally demonstrated.