Extract LUT Logics from a Downloaded Bitstream Data in FPGA

This paper presents a logic resynthesizing of FPGA from a downloaded bitstream data for Xilinx 7 series FPGA. This study focuses on the LUT logic reconstructing, which is a primitive logic unit in FPGA. The approach generates all possible logic for a LUT trying to various examples. The generated files are compared with each other that are used to construct the truth table of the LUT. The proposed algorithm extracts the logic configuration by analyzing the bitstream and comparing it with the constructed truth table. The resynthesized circuits provide the input and output pin information assigned in the LUT. The algorithm can be expanded to the previous version of Xilinx 7 series. This study will be helpful for security enhancing of FPGA and development of logic synthesis technique.