A novel approach to reduce interconnect complexity in ANN hardware implementation

Hardware implementation of large digital artificial neural networks is limited by several constraints, such as the complexity of neural interconnections. This paper presents a novel approach to solve the interconnection problem for artificial neural networks, using reconfigurable computing and dynamically reconfigured FPGAs in a new computational way: the execution patterns (EPs). The EPs allow reducing the influence of interconnections through the removal of data transport via busses. Thus, data transport is not necessary to perform the computation and interconnection complexity between neurons is reduced.