A 10-GS/s track-and-hold circuit for a 7-bit Square Kilometre Array ADC in 65-nm

The design and measurement of a broadband 10-GS/s 65-nm CMOS track-and-hold (T/H) circuit are discussed. The measured 3-dB bandwidth of the T/H circuit is 4.5 GHz with a DC gain of −1 dB, a spurious-free dynamic range (SFDR) of >41 dB and a total harmonic distortion (THD) of >40 dBc up to Nyquist when sampling at a 10-GS/s rate. The measured power consumption of the core circuit is 142 mW from a 1.3-V supply. This T/H circuit is designed to operate with an input voltage range of 0.3 Vpp.