Failure analysis on plasma charging induced damage due to effect of circuit layout & device structure marginality

Failure analysis on low yield cases revealed different degrees of fused polysilicon gate damage on specific CMOS circuit layout and device structure. Non-uniformity of plasma density during plasma related process has induced trapped charges in the gate oxide especially on circuit layout with large metal line perimeters and small poly gate structure. Trapped charges could become the catalyst to cause fused polysilicon gate when it is subjected to non-optimized external electrical voltage biasing condition which carries large voltage spike during transient state when integrated chip is powered up. A series of investigation was carried out in this paper to explore the failure mechanisms seen on these circuit design layouts and device structures.