Interpretation of Defect States in Sputtered IGZO Devices Using I-V and C-V Analysis

Capacitance-voltage (C-V) analysis is a valuable tool in separating the influence of material and interface defects from other factors that influence transistor operation. Thin-film transistors and interdigitated capacitors fabricated using sputtered IGZO have been studied to enhance the interpretation of defect states. Interdigitated capacitors are representative of the TFT channel region, and large-area designs provide a high capacitance swing from depletion to accumulation. Alumina was applied for back channel passivation, with annealing performed at 400 °C in oxidizing ambient conditions. Both I-V and C-V results were used with TCAD device simulation to develop a refined material and device model.