Numerical Analysis of the Electrical Characteristics of Gate Overlapped Lightly Doped Drain Polysilicon Thin Film Transistors

Polycrystalline silicon (polysilicon) thin film transistor (TFT) technology is emerging as a key technology for active matix liquid crystal displays, allowing the integration of both active matrix and driving circuitry on the same substrate. However, conventional self-aligned polysilicon TFTs present several undesired effects in the electrical characteristics, including large off-currents, kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and drain field relief is essential. Among the different structures proposed to reduce the drain field, the gate overlapped lightly doped drain (GOLDD) structure appears to have a number of advantages. In this work we investigate the electrical characteristics of GOLDD polysilicon TFTs by using 2-dimensional (2D) numerical analysis. From a close analysis of the output characteristics, we have distinguished two saturation regimes: the first related to the conventional formation of the pinch-off region near the LDD, the second one, occurring at higher source-drain voltages, related to the depletion of the LDD region. Impact ionization effects have been also analysed and kink effect in GOLDD structure has been found to be associated with the parasitic bipolar transistor action, similarly to silicon-on-insulator (SOI) devices. At very high source-drain voltages, avalanche breakdown occurs, due to impact ionization occurring at both channel/LD-region and LD-region/n+ region junctions.