High-resolution patterning for panel level packaging

More-than-Moore approaches to improve system performance have been a hot topic for a more than a decade as a way to maximize the efficiency and increase the bandwidth of high performance computing systems. Fan-Out packaging that realizes submicron Redistribution Lines (RDL) and large die sizes is one technology that can help enable complex heterogeneous integration for applications including Artificial Intelligence (AI) and autonomous driving. For systems requiring large package sizes, Panel Level Packaging (PLP) can offer efficiency and cost advantages over Wafer Level Packaging (WLP). PLP however poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first patterning exposure tool (stepper) capable of submicron resolution on 500 mm panels. The panel exposure tool is equipped with wide-field projection optics that offer a large 52 mm × 68 mm image field and a 0.24 NA that is optimum for submicron resolution. The stepper also features an updated panel handling system for processing up to 515 × 515 mm panels. In this paper, we will report on our study of fine patterning on rectangular panels using the submicron resolution panel stepper and will introduce technology innovations supporting advanced heterogeneous integration. Our study researched photoresist material performance and slit-coating uniformity challenges we identified through collaboration with resist vendors and slit-coating equipment manufacturers. We will report on the results of our collaborative study and will discuss current and future PLP advantages, challenges and solutions.