Prediction of System Performance Based on Component Jitter and Noise Budgets

Conventional ways of summing component specifications to balance voltage and timing budgets are increasingly problematic as data rates continue to scale higher for high speed links. For instance, performance degradation caused by transmitter jitter is more severe than that caused by receiver jitter due to jitter coloring by the passive channel. Furthermore, certain jitter components could interact in the system so it is inaccurate to treat them as independent variables. A system voltage and timing budgeting process hence requires a sophisticated method to accurately predict the overall system performance based on the component specifications. With the recent introduction of a statistical CAD tool, the impact of each individual component, including both deterministic and random jitter, can be co-simulated [l]-[3]. This paper demonstrates the usage of this statistical CAD tool for modeling component budgets. We verify the accuracy of our modeling approach by correlating with a FlexIO reg parallel link interface. Then, we apply the proposed methodology to a PCI Express reg bus system to estimate the system performance based on published component jitter specification.