High-speed and logic-compatible split-gate embedded flash on 28-nm low-power HKMG logic process

We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um 2 ) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) and robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture and scaling of word-line (WL) transistor. New type of high-voltage transistor with LDD-first scheme is applied to enable further scaling of decoder block in Flash IP. Digital-Vdd (1.0V) read operation is used by lowering threshold voltage (V th ) of HV transistor without sacrificing break-down during Flash P/E operation. By using module process concept, the existing RF and logic IP is reused without modification.