A switched-current double sampling bilinear z-transform filter technique

A filter technique, based on an integrator/summer which performs the bilinear z-transform and achieves two samples per clock period, is described. The operation of the integrator/summer is analysed and this is supported by simulation. As an example, a 3rd order lowpass elliptic ladder filter is designed. Measurement of an IC designed for a cut-off frequency of 8 MHz with sampling at 80 MHz confirm the technique and indicate that operation at sample frequencies beyond 100 MHz is feasible. >