Synthesis of Synchronous Gray Code Counters by Combining Mentor Graphics HDL Designer and Xilinx VIVADO FPGA Flow

Increased complexity of circuits builds more challenge for testing the functionality as well as errors in the circuit. One of the challenges in testing is increased power requirements during test mode. This paper proposes a scheme for test pattern generation based on gray code. A new approach of combining Mentor Graphics HDL Design and Xilinx VIVADO is used for generating the proposed test pattern generator. Parameters like area, power are analyzed and compared with the corresponding gate level models.