A 1 V, 10.4 mW low power DSP core for mobile wireless use

We designed a 1 V, 50 MHz, 16-bit DSP core using a 0.25-/spl mu/m Dual Vt Library, SRAM, and Mask ROM tailored for 1 V operation. The core architecture was enhanced using an alternate MAC to recover slower circuitry. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. A power simulation with a CODEC firmware showed 10.4 mW, about a quarter of a standard DSP.