Novel capacitor structure using sidewall spacer for highly reliable ferroelectric random access memory device

Since ferroelectric capacitors prepared by 1-mask etching are degraded after the etching, we systematically investigated the origin of the degradation. It was found that the major degradation originates from the formation of the nonstoichiometric and amorphorized Pb(ZrxTi1-x)O3 (PZT) layer on the sidewall of the PZT film during etching of the bottom electrode (BE). Therefore, to eliminate the undesired etch-damaged layer, we developed a novel etching technology using a ferroelectric (FE) sidewall spacer, which results in the enhancement of the remnant polarization after completing the capacitor etching process. Using the novel FE sidewall spacer, the sensing margin of bit-line-developed voltage was improved to 400 mV, which can guarantee highy reliable high-density ferroelectric random access memory (FRAM) devices.