Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure

Medium volume VeSFET-based ASICs can fill the gap between high cost microprocessors and low performance FPGAs. Circuits can be customized onto pre-manufactured VeSFET canvases by properly designed interconnects. In this paper, we propose chain canvases , a family of VeSFET canvases for which CMOS-oriented EDA tools can be easily adapted. Footprint area, wire length, via usage, performance and power are compared between chain canvas- and basic canvas-mapped benchmarks. Experimental results show that chain canvas-mapped circuits outperform those mapped to basic canvases.