Reduce the energy consumption of Uncore circuits of a processor

A multi-core processor, comprising: a plurality of cores (110) and an uncore, said the uncore having at least one cache memory, a plurality of logic units, comprising a router (130), a power control unit (150) and at least one further logic unit, wherein the power control unit (150) comprises at least one of the plurality of logic units and the target tick control a cache memory of the uncore at least when the multi-core processor is in a low power state after a first time period has occurred in which the plurality of logic units was permanently cleared transactions prevented after the transactions on a first channel were, and after a second time period has occurred in which the plurality of logic units was continuously emptied of transactions, wherein the power control unit is designed to prevent incoming transactions from one or more channels outside of the socket prior to the clock controlling.