Partial Scan using Modified Testcube Analysis Algorithm

In modern era transistor size is becoming too small, currently it is 20 nanometer and still to decrease in near future. Thus, silicon chips are more capable to accommodate large number of logical nodes on it and also for making complex integrated circuit (IC). As the complexity of the circuit increases partial scan becomes more vulnerable for low test coverage and high computational requirement. Presently there are no specific methods or guidelines which exactly instruct the conversion of scannable flops to non scannable flops. So Increasing complexity of IC‟s has forced the industry to abandon partial scan, which necessitates a computationally demanding and unaffordable sequential ATPG, and rather to adopt full scan despite its costs. Full scan provides high test coverage but it has several draw backs like it increases the cost of scan, increases the area overhead, decreases design performance, increases power consumption of circuit, increases delay in the circuit. In this paper a modified Testcube analysis algorithm which enables the tester to use partial scan with high test coverage is proposed. The Proposed modified Testcube analysis algorithm specifies a method to select certain number of flops which can be excluded from the scan process and to reduce the area complexity of the design. The selection of flop which can be converted to non scannable flop is based on the justification of block of that flop. The justification block is decided by the finding the maximum length path between the flop and its associated driving flops. After getting the justification block, its relative dependency graph is generated for each scan chain and the flops which are having minimum dependency in the graph, which are selected as convertible flops.