First Transistor Demonstration of Thermal Atomic Layer Etching: InGaAs FinFETs with sub-5 nm Fin-width Featuring in situ ALE-ALD

For the first time, thermal atomic layer etching (ALE) on InGaAs-based III-V heterostructures is demonstrated. Also, we report the first transistors fabricated by the thermal ALE technique in any semiconductor system. We further highlight one unique advantage of thermal ALE: its integration with atomic layer deposition (ALD) in a single vacuum chamber. Using in situ ALE-ALD, we have fabricated the most aggressively scaled self-aligned In 0.53 Ga 0.47 As n-channel FinFETs to date, featuring sub-5 nm fin widths. The narrowest FinFET with $\mathrm{W_{f}}=2.5$ nm and $\mathrm{L_{g}} =60$ nm shows $\mathrm{g}_{\mathrm{m}}=0.85\ \text{mS}/\mu \mathrm{m}$ at $\mathrm{V}_{\text{ds}}=0.5$ V. Devices with $\mathrm{W_{f}}=18$ nm and $\mathrm{L_{g}}=60$ nm demonstrate $\mathrm{g_{m}}=1.9\ \ \text{mS}/\mu \mathrm{m}$ at $\mathrm{V}_{\text{ds}}=0.5$ V. Subthreshold swings averaging $\mathrm{S}_{\text{lin}}=70$ mV/dec and $\mathrm{S}_{\text{sat}}=74$ mV/dec across the entire range of W f , at minimum $\mathrm{L_{g}}=60$ nm have been obtained. These are all record results. The transistors demonstrated here show an average 60% gm improvement over devices fabricated through conventional techniques. These results suggest a very high-quality MOS interface obtained by the in situ ALE-ALD process.