Low-Power Reconfigurable FFT/IFFT Processor

Fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) are being applied in various fields of digital signal processing (DSP) applications because of the advanced technology of VLSI. In recent communication system, orthogonal frequency division multiplexing (OFDM) is the most important FFT and IFFT application. FFT/IFFT processors in these communication systems consume high power, rendering the system inefficient. OFDM-based UWB systems IEEE 802.15.4a employ 64 point and IEEE 802.11a-based systems employ 128/64 point and, therefore, we designed 128/64 point FFT/IFFT processor. The radix-25 algorithm that we used reduces the number of non-trivial multiplications. By implementing clock gating technique and a low-power multiplier, we propose to design a low power, reconfigurable, variable-length FFT/IFFT processor. The simulation of the design was done using ModelSim and power consumption has been analyzed with 180 nm CMOS technology using Cadence Encounter tool. The power consumed by the processor without clock gating is 58.27 mW and with clock gating is 2.13 mW.