FPGA-based logical operation search method and system

The invention discloses an FPGA-based logical operation search method. The method includes the steps of extracting super-quintuple information from an input network message; setting different fields for the super-quintuple information of the network message; comparing the fields of the super-quintuple information with a comparison range to generate corresponding identifier bits; from the identifier bits of the fields, generating a vector with logic bits and operations among elements; decomposing the vector to generate a plurality of sub-vectors according to the number of logics or operations; dividing a TCAM into the corresponding amount of areas according to vector dimensions required by search; configuring an entry of each area according to a descending order of effective states; correspondingly searching for the number of effective bits in the sub-vectors and the number of effective states in the TCAM, generating search result bits, and subjecting the result bits to logics or operations to generate final identifier bits to complete the search; passing the matched message and abandoning the failed message.