Degradation of Polycrystalline Silicon TFT CMOS Inverters under AC Operation

Degradation of polycrystalline silicon (poly-Si) thin-film transistor (TFT)-based CMOS inverters under AC operation is studied. Based on a previous drain current model of poly-Si TFTs including the kink effect, the voltage transfer characteristics of both fresh and stressed inverters are well described. It is determined that hot carrier of the n-TFT and negative bias temperature instability of the p-TFT are competing degradation mechanisms controlling the observed two-stage degradation of the inverter. Based on such mechanisms, degradation of inverter under various AC operation conditions can be qualitatively predicted. It is found that under given frequency and amplitude of the input pulse voltage, inverter's degradation can still be effectively suppressed by increasing the pulse falling time, and/or decreasing the low voltage duration.