A calibrated pathfinding model for signal integrity analysis on interposer

A calibrated pathfinding on silicon interposer is presented for exploring the impact of interconnect geometries on signal integrity. ABCD matrix-based model and single bit method are used for the pathfinding by estimating the worst-case eye opening. Experiment-based eye-diagrams using measured S-parameters on the fabricated silicon interposer are compared with the pathfinding showing 6% max difference. The pathfinding utilizes to optimize design parameters with 99% reduce of simulation time. It also extends for the optimization of parameters in multi interconnects considering mutual effects as well as crosstalk.