A Direct ΔΣ Receiver with Current-Mode Digitally-Synthesized Frequency - Translated RF Filtering

A 0.5-2.75 GHz, 10 MHz bandwidth, direct ΔΣ receiver architecture that uses a mixed-signal technique to eliminate the baseband channel select filter and provides higher order filtering at RF front-end using a single feedforward op-amp is described. The RF -to-bits system uses feedback FIR-DACs and impedance upconversion to provide equivalent 2 nd order analog filtering before the ΔΣ ADC. Measurements demonstrate up to 38 dB gain for the inband signal, with up to 9 dB improvement for the out-of-band IIP3 and a peak SNDR of 35 dB. The receiver is designed in a 65 nm CMOS technology, has an active area of 0.15 mm 2 , and consumes 9.3-16.2 mW of power, with a total energy efficiency of 5.5-9.8 pJ/lvl across the centre frequency range.