Effects of cobalt silicidation and postannealing on void defects at the sidewall spacer edge of metal–oxide–silicon field-effect transistors

The void formation at the edge of the sidewall spacer during postannealing is favorable in reducing both the number of excess silicon vacancies generated in the silicon substrate during silicidation, and the tensile stress concentrated at the edge of the metal-oxide-silicon field-effect transistor (MOSFET) sidewall spacer. The observation of void growth with the postannealing time supports this hypothesis. The observed void shape agrees well with a numerical simulation driven by the minimization of the interfacial free energy. The void serves as a resistance in the current–voltage characteristics of MOSFET devices.