Systematic Design of multi-phase clock-generators for low-jitter edge-driven switching based on asynchronous machines for multi-channel time-interleaved ADC's

The aim of this master’s thesis was to present the low-phase skew and low-jitter solutions for high-speed time-interleaved discrete-time systems. The emphasis of the work was put on different clock generator architectures used in high-throughput Analog to Digital Converters as well as in Digital-Analog Converters and Sample-and-Hold circuits. Among the proposed structures are dedicated PLLs, DLLs, synchronous and asynchronous machines, as well as solutions employing calibration techniques. The author of this thesis presented two approaches that introduced some innovation in matter of precision and robustness against PVT corners. One of them uses local feedback in additional biasing devices to make the system more reliable in different work conditions. The other one is based on asynchronous state machines which, with use of a design tool dedicated to this kind of systems, could be evolved into a form that relaxes the speed of a single operation while maintaining the overall throughput. In both cases the aim was to overtake the already existing solutions in matter of parameters that are most critical for this kind of circuits (e.g. jitter, phase skew, power dissipation). The designing procedures were described and the final circuits were simulated in order to obtain the values of the mentioned parameters for comparison, based on which conclusions could be drawn and possibilities of future work stated.