A NoC-based Sparse Matrix Multiplication System

Sparse matrix multiplication (SMM) is widely used in many vital scientic and engineering computations, such as least-squares problems, eigenvalue problems, partial dierential equations, and image reconstruction. However, it is a very time-consuming process and the irregular structure of sparse matrices usually causes general-purpose processors to perform poorly and to suer cache misses severely. In this paper, we develop an SMM system based on network-on-a-chip (NoC) technology to parallelize the needed computations. To facilitate the load balancing and eciency of packet distribution on the proposed SMM system, a method of mapping and partitioning a large