Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls
2017
Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or “fins”). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor–liquid–solid growth and vertical facet-selective noncatalytic vapor–solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm2) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 108, 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities...
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
63
References
20
Citations
NaN
KQI