Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence

This paper deals with transistor sizing based static power optimization for multi-stage CMOS circuits using swarm intelligence algorithm. The overall circuit performance is improved by optimizing the individual basic cell performances. Optimized cells are re-used at places with similar circuit scenarios thereby reducing the number of variables to work with. At each stage of execution, the algorithm generates multiple sizing options for basic cells with varying power-delay specifications to choose from. This work proposes a dual sizing approach for critical and non-critical path cells. The overall process has low circuit dependence and has been applied on a wide range of single and multi-stage circuits (including ISCAS benchmark circuits). The approach considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55°C to 125°C) and supply voltage (±10%) variations for robust sizing solutions. Results show leakage reductions up to 63.6%.