Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules

In this paper, a concept for generating tests for RISC processors is proposed relying solely on functional information such as the instruction set without any knowledge of the implementation details. For the first time, the effect-cause idea, instead of the traditional cause-effect fault driven approach, is applied for test generation. For implementing the effect-cause idea, a novel high-level constraint-based functional fault model is developed. This novelty made it possible to extend the classical Stuck-At Fault (SAF) model, applied so far in evaluating the quality of processor testing, not only to a large class of structural faults, such as conditional SAF, bridging faults, delay faults etc., but also to the functional faults similar to those covered by the March algorithm in memory testing. By experimental research it was demonstrated that the test quality of the proposed implementation-independent test generation method produces test sequences with comparable or better fault coverages for SAF and Transition Delay Faults (TDF) than known methods utilizing knowledge about the implementation details.