A new method for post-etch OPC modeling to compensate for underlayer effects from integrated wafers

In this paper, we demonstrate a new methodology for post-etch OPC modeling to compensate for effects of underlayer seen on product wafers. Current resist-only OPC models based on data from flopdown wafers are not always accurate enough to deliver patterning solutions with stringent critical dimension requirements in 45/32nm technology node. Therefore it is necessary to include an etch model into the OPC correction. Both litho and etch model were built using flopdown and integrated wafers to compensate for topography, differential etch due to different underlayer substrate based on local geometry and local loading. The wafer data based on such OPC keyword show significant decrease of critical dimensions offsets of device macros from long poly-line nested structures for gate level. We will compare wafer data from two different OPC model versions built from flopdown and integrated wafer. We will also discuss modeling options in terms of two layer test masks for future technologies.