Carry-skip adder

A carry-skip adder (also known as a carry-bypass adder) is an adder implementation that improves on the delay of a ripple-carry adder with little effort compared to other adders. The improvement of the worst-case delay is achieved by using several carry-skip adders to form a block-carry-skip adder. A carry-skip adder (also known as a carry-bypass adder) is an adder implementation that improves on the delay of a ripple-carry adder with little effort compared to other adders. The improvement of the worst-case delay is achieved by using several carry-skip adders to form a block-carry-skip adder. The worst case for a simple one level carry-ripple-adder occurs, when the propagate-condition is true for each digit pair ( a i , b i ) {displaystyle (a_{i},b_{i})} . Then the carry-in ripples through the n {displaystyle n} -bit adder and appears as the carry-out after τ C R A ( n ) ≈ n ⋅ τ V A {displaystyle au _{CRA}(n)approx ncdot au _{VA}} . For each operand input bit pair ( a i , b i ) {displaystyle (a_{i},b_{i})} the propagate-conditions p i = a i ⊕ b i {displaystyle p_{i}=a_{i}oplus b_{i}} are determined using an XOR-Gate (see ). When all propagate-conditions are true, then the carry-in bit c 0 {displaystyle c_{0}} determines the carry-out bit. The n-bit-carry-skip adder consists of a n-bit-carry-ripple-chain, a n-input AND-gate and one multiplexer.Each propagate bit p i {displaystyle p_{i}} , that is provided by the carry-ripple-chain is connected to the n-input AND-gate. The resulting bit is used as the select bit of a multiplexer that switches either the last carry-bit c n {displaystyle c_{n}} or the carry-in c 0 {displaystyle c_{0}} to the carry-out signal c o u t {displaystyle c_{out}} . This greatly reduces the latency of the adder through its critical path, since the carry bit for each block can now 'skip' over blocks with a group propagate signal set to logic 1 (as opposed to a long ripple-carry chain, which would require the carry to ripple through each bit in the adder).The number of inputs of the AND-gate is equal to the width of the adder. For a large width, this becomes impractical and leads to additional delays, because the AND-gate has to be built as a tree. A good width is achieved, when the sum-logic has the same depth like the n-input AND-gate and the multiplexer. The critical path of a carry-skip-adder begins at the first full-adder, passes through all adders and ends at the sum-bit s n − 1 {displaystyle s_{n-1}} . Carry-skip-adders are chained (see block-carry-skip-adders) to reduce the overall critical path, since a single n {displaystyle n} -bit carry-skip-adder has no real speed benefit compared to a n {displaystyle n} -bit carry-ripple-adder. The skip-logic consists of a m {displaystyle m} -input AND-gate and one multiplexer.