Planar process

The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The planar process was developed by Jean Hoerni in 1959, building on the surface passivation method developed by Mohamed Atalla in 1957. Hoerni's planar process was the basis for Robert Noyce's invention of the silicon integrated circuit in 1959. The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The planar process was developed by Jean Hoerni in 1959, building on the surface passivation method developed by Mohamed Atalla in 1957. Hoerni's planar process was the basis for Robert Noyce's invention of the silicon integrated circuit in 1959. The key concept is to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allows the use of a series of exposures on a substrate (silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization, and the concept of p–n junction isolation, it is possible able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule. The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together. In 1957, Bell Telephone Laboratories (BTL) researcher Mohamed 'John' Atalla proposed a semiconductor device fabrication method, coating a silicon wafer with an insulating layer of silicon oxide so that electricity could reliably penetrate to the conducting silicon below. By adopting a method of growing a layer of silicon dioxide on top of a silicon wafer, Atalla was able to overcome the surface states that prevented electricity from reaching the semiconducting layer. This method is known as surface passivation. He studied the passivation of p-n junctions by oxide, and published his experimental results in 1957 BTL memos. Atalla's surface passivation method was later the basis for two inventions in 1959: the MOS transistor by Atalla and Dawon Kahng, and the planar process by Jean Hoerni. At a 1958 Electrochemical Society meeting, Atalla presented a paper about the passivation of PN junctions by oxide (based on his 1957 BTL memos), and demonstrated silicon dioxide's passivating effect on a silicon surface. Jean Hoerni attended the same meeting, and was intrigued by Atalla's presentation. Hoerni came up with a 'planar idea' one morning while thinking about Atalla's device. Taking advantage of silicon dioxide's passivating effect on the silicon surface, Hoerni proposed to make transistors that were protected by a layer of silicon dioxide. The planar process was developed by Jean Hoerni, one of the 'traitorous eight', while working at Fairchild Semiconductor, with a first patent issued 1959. Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule. In 1959, Robert Noyce built on Hoerni's work with his conception of an integrated circuit, which added a layer of metal to the top of Hoerni's basic structure to connect different components, such as transistors, capacitors, or resistors, located on the same piece of silicon. The planar process provided a powerful way of implementing a silicon integrated circuit that was superior to earlier non-silicon conceptions of the integrated circuit. Early versions of the planar process used a photolithography process using near-ultraviolet light from a mercury vapor lamp.As of 2011, small features are typically made with 193 nm 'deep' UV lithography.Some researchers use even higher-energy extreme ultraviolet lithography.