Wright etch

The Wright etch (also Wright-Jenkins etch) is a preferential etch for revealing defects in <100>- and <111>-oriented, p- and n-type silicon. It was developed by Margaret Wright Jenkins in 1976 while working in research and development at Motorola Inc. It was published in 1977. This etchant reveals clearly defined oxidation-induced stacking faults, dislocations, swirls and striations with minimum surface roughness or extraneous pitting. These defects are known causes of shorts and current leakage in finished semiconductor devices (such as transistors) should they fall across isolated junctions. A relatively low etch rate (~1 micrometre per minute) at room temperature provides etch control. The long shelf life of this etchant allows the solution to be stored in large quantities. The Wright etch (also Wright-Jenkins etch) is a preferential etch for revealing defects in <100>- and <111>-oriented, p- and n-type silicon. It was developed by Margaret Wright Jenkins in 1976 while working in research and development at Motorola Inc. It was published in 1977. This etchant reveals clearly defined oxidation-induced stacking faults, dislocations, swirls and striations with minimum surface roughness or extraneous pitting. These defects are known causes of shorts and current leakage in finished semiconductor devices (such as transistors) should they fall across isolated junctions. A relatively low etch rate (~1 micrometre per minute) at room temperature provides etch control. The long shelf life of this etchant allows the solution to be stored in large quantities.