Anyan Du

Chinese Academy of Sciences

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Trends

Author Order

Document Type

Co-Authors

Chunxiang Zhu

National University of Singapore

Albert Chin

National Yang Ming Chiao Tung University

Dim‐Lee Kwong

Agency for Science, Technology and Research

D.S.H. Chan

Centre d'Études et de Recherches sur le Développement International

Yee‐Chia Yeo

Taiwan Semiconductor Manufacturing Company (Taiwan)

H.Y. Yu

Southern University of Science and Technology

M.F. Li

Southern University of Science and Technology

Ching‐Hsuan Tung

Cornell University

Jagar Singh

GlobalFoundries (United States)

S.J. Lee

National University of Singapore

Cooperative Institutions

National University of Singapore

117

Institute of Microelectronics

Agency for Science, Technology and Research

Chinese Academy of Sciences

Institute of Microelectronics

Singapore Science Park

University of Chinese Academy of Sciences

Nanyang Technological University

GlobalFoundries (Singapore)

Institute of Materials Research and Engineering

Author Statistics

Papers

Citation

H-Index

i-10 index

Research Field

High Performance ALD HfO 2-Al 2O 3 Laminate MIM Capacitors for RF and Mixed Signal IC Applications

International Electron Devices Meeting (2003)

Hang Hu Shi Jin Ding H.F. Lim Chunxiang Zhu M. F. Li

for RF and Mixed Signal IC Applications Hang Hu, Shi-Jin Ding, HF Lim, Chunxiang Zhu, M.F. Li , S.J. Kim, XF Yu, JH Chen, YF Yong, Byung Jin Cho, D.S.H. Chan, Subhash C Rustagi, MB Yu, CH Tung, Anyan Du, Doan My, PD Foo, Albert Chin, Dim-Lee Kwong SNDL, Dept. of ECE, National Univ. of Singapore, Singapore, 119260 Tel: 65-6874 8930, Fax: 65-6779 1103 Email: elezhucx@nus.edu.sg Institute of Microelectronics, Singapore, 117685, Dept. of Electronics Eng., National Chiao Tung Univ., Taiwan Dept. of Electrical & Computer Eng., Univ. of Texas, Austin, TX 78712, USA

Microelectronics

Source

Cite

Citations (9)

Investigation of silicon-germanium fins fabricated using germanium condensation on vertical compliant structures

Applied Physics Letters (2005)

Tsung-Yang Liow Kian-Ming Tan Yee‐Chia Yeo Ajay Agarwal Anyan Du

We report the formation of defect-free SiGe vertical heterostructures using Ge condensation on vertical SiGe structures. To evaluate the effectiveness of substrate compliance in vertical structures, SiGe fins of various widths were subjected to Ge condensation. This formed vertical fin heterostructures comprising a SiGe core region sandwiched by Ge-rich regions. Using cross-sectional transmission electron microscopy (TEM), wide fins were found to contain more dislocations than narrower fins, in which we observed few or no dislocations. Lattice strain analysis using high-resolution TEM image analysis was used to confirm that strain relaxation has occurred. In the wide fins (noncompliant substrate), strain relaxation was dislocation mediated. In the narrow fins, substrate compliance enabled strain relaxation in the Ge-rich layer with reduced dislocation formation. Hence, we also demonstrated the formation of a strain-relaxed homogeneous SiGe fin (∼90% Ge concentration) with no observable dislocations.

Stress relaxation

10.1063/1.2151257

Cite

Citations (25)

Strain Engineering of Ultra-Thin Silicon-on-Insulator Structures Using Ion Implant

Yinjie Ding Ran Cheng Qian Zhou Anyan Du Nicolas Daval

In this paper, we report a novel way of introducing strain in Ultra-Thin Body and Buried-Oxide (UTBB) SOI structures by Ge implant into the underlying Si substrate and the formation of localized SiGe regions underneath the buried oxide (BOX) by solid-phase epitaxy (SPE).

Strain engineering

Strain (injury)

Silicon oxide

10.1109/istdm.2012.6222470

Cite

Citations (0)

Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors

Applied Physics Letters (2005)

Kah‐Wee Ang King-Jien Chui Vladimir Bliznetsov Chih-Hang Tung Anyan Du

We report the characterization of strain components in transistor structures with silicon–germanium (Si0.75Ge0.25) and silicon–carbon (Si0.99C0.01) stressors grown by selective epitaxy in the source and drain regions. The spacing between the source and drain stressors is 35nm. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The lateral strain component εxx and the vertical strain component εzz were derived from the (220) and (002) reflections in the diffractogram, respectively. SiGe source and drain stressors lead to lateral compressive strain and vertical tensile strain in the Si channel. On the other hand, the SiC source and drain stressors give rise to lateral tensile strain and vertical compressive strain in the Si channel, an effect complementary to that of SiGe source∕drain stressors. The results of this work will be useful for channel strain engineering in complementary metal-oxide-semiconductor transistors.

Strain engineering

Strained silicon

10.1063/1.1871351

Cite

Citations (107)

Integrated Optical Sensing and Communication (IOSAC) System Based on Hybrid‐Waveguide Structures

Advanced Materials Technologies (2023)

Xiangpeng Ou Ying Qiu Ming Luo Junjie Li Xiaobin He

Abstract Advanced silicon photonic technologies enable integrated optical sensing and communication (IOSAC) in real time for the emerging application requirements of simultaneous sensing and communication for next‐generation networks. Herein, an IOSAC system is proposed and demonstrated on the silicon nitride (Si 3 N 4 ) photonics platform. The IOSAC devices leveraging microring resonators excel in real‐time monitoring of analyte fluctuations and efficiently transmit this data to the terminal, positioning them as viable alternatives to bulk optics in applications that demand both high precision and speed. By directly integrating Si 3 N 4 ring resonators with optical communication networks, simultaneous sensing and optical communication are demonstrated by an optical signal transmission experimental system using especially filtering amplified spontaneous emission spectra. The refractive index (RI) sensing ring with a sensitivity of 172 nm RIU −1 , a figure of merit (FOM) of 1220, and a detection limit (DL) of 8.2 × 10 −6 RIU is demonstrated. Simultaneously, the 1.25 Gbps optical on‐off‐keying (OOK) signal is transmitted at the concentration of different NaCl solutions, indicating the bit‐error‐ratio (BER) decreases with the increase in concentration. The novel IOSAC technology shows the potential to realize high‐performance simultaneous biosensing and communication in real time and further accelerate the development of IoT and 6G networks.

Figure of Merit

SIGNAL (programming language)

Waveguide

10.1002/admt.202300998

Cite

Citations (1)

Schottky s/d MOSFETs with high-K gate dielectrics and metal gate electrodes

Shiyang Zhu Jingde Chen H.Y. Yu S. J. Whang J.H. Chen

Bulk Schottky silicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0 /spl sim/ 2.5nm HfO/sub 2/ gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi silicide show excellent electrical performance of I/sub on//I/sub off//spl sim/ 10/sup 7/ - 10/sup 8/ and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi/sub 2-x/ silicide have also demonstrated a very promising characteristic with a recorded high I/sub on//I/sub off/ radio of /spl sim/ 10/sup 7/ and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.

Metal gate

Subthreshold slope

High-κ dielectric

Subthreshold conduction

10.1109/icsict.2004.1434952

Cite

Citations (0)

Study of upstream electromigration bimodality and its improvement in Cu low-k interconnects

Wenjing Liu Y.K. Lim F. Zhang H. Liu Yinghong Zhao

The bimodality of upstream electromigration (EM) failures in the dual damascene structure of 45 nm Cu interconnection process with low-k material is investigated, and the improvement is demonstrated. Two major early failure modes with voids forming in via or at the chamfer of via-trench transition area are revealed and attributed to liner process weakness at the respective locations, which can be reduced and eliminated with optimized via and chamfer aspect ratios (ARs) defined by the dual damascene profile. Dielectric thickness, trench etch depth, via critical dimension (CD), chamfer of via-trench transition profile etc. can serve as the tuning factors for the upstream EM bimodality improvement. However, a balance between EM, time-dependent dielectric breakdown (TDDB) and resistance-capacitance (RC) performance need to be achieved.

Chamfer (geometry)

Copper interconnect

Electromigration

Bimodality

Low-k dielectric

10.1109/irps.2010.5488709

Cite

Citations (6)

Stacked Gate-All-Around Nanosheet Transistors with Full-Air-Spacers for Reducing Parasitic Capacitance to Improve Device and Circuit Performance

Microelectronics Journal (2024)

Lianlian Li Lei Cao Xuexiang Zhang qingkun li Zhenhua Wu

Nanosheet

Parasitic capacitance

Parasitic element

10.1016/j.mejo.2024.106535

Cite

Citations (0)

A TaN-HfO -Ge pMOSFET With Novel SiH Surface Passivation

Nan Wu Qingchun Zhang Chunxiang Zhu D.S.H. Chan Anyan Du

Passivation

Source

Cite

Citations (1)

Phase change random access memory cell with superlattice-like structure

Applied Physics Letters (2006)

Tow Chong Chong Luping Shi Rong Zhao P.K. Tan J. M. Li

A superlattice-like structure (SLL) incorporating two nonpromising phase change materials was applied to phase change random access memory (PCRAM) cell. A properly designed SLL structure could balance both the phase change speed and stability of a PCRAM. Moreover, SLL PCRAM cells exhibited lower programming current and fast working time of 5ns. The main reason for the excellent performances is due to the much lower thermal conductivity of the SLL material compared to that of bulk materials. The thermal conductivity of eight SLL layers cycle was found to be smaller than 30% of that of single layer material.

Phase-change memory

Thermal Stability

10.1063/1.2181191

Cite

Citations (233)