The speed degradation in CMOS circuits with the supply voltage reduction is an important obstacle in the scale down of supply voltage. Thus, many attempts to reduce the gate delay have been tried using the dynamic threshold scheme. However, they have limitations in the operation voltage and large leakage current. We propose a new type of SOI inverter gate which has considerably shortened circuit delay with similar energy consumption in the conventional SOI CMOS circuit at low voltage operation. It uses the positive-body bias effect that enhances drain currents when the body is biased positively. The operation principle of the proposed gate, the optimal circuit and device conditions studied by simulations, and the fabrication and measurement data are reported in this paper.
The drain current enhancement due to the velocity overshoot effects is found to be due to the electron velocity enhancement at the source end. Based on this observation, a new analytic model is proposed and verified by two-dimensional (2-D) simulations and experiments. From the results of the verifications, we conclude that our model predicts the drain current enhancement due to the velocity overshoot effects reasonably well. The effects of the device parameters, such as gate oxide thickness and channel doping concentration, on the drain current enhancement ran be readily found in our model.
Noise in homogeneous extrinsic semiconductor samples is calculated due to distributed diffusion noise sources. As the length of the device shrinks at a fixed bias voltage, the ac-wise short-circuit noise current shows excess noise as well as thermal noise spectra. This excess noise behaves like a full shot noise when the channel length becomes very small compared with the extrinsic Debye length. For the first time, the analytic formula of the excess noise in extrinsic semiconductors from velocity-fluctuation noise sources is given for finite frequencies. This formula shows the interplay between transit time, dielectric relaxation time, and velocity relaxation time in determining the terminal noise current as well as the carrier density fluctuation. As frequency increases, the power spectral density of the excess noise rolls off. This formula sheds light on noise in nanoscale MOSFETs where quasi-ballistic transport plays an important role in carrier transport and noise.
In this paper, the Monte Carlo method is applied to uniform and n/sup +/-n/sup -/-n/sup +/ structures of silicon to study the behavior of tail electrons and to develop a new set of hydrodynamic equations based on tail electron statistics. Each term in these equations is calibrated under both nonhomogeneous and homogeneous electric fields. Terms associated with surface integral of the carriers and carrier momentum over an iso energy surface: (/spl Escr/=/spl Escr//sub th/) are introduced. The new tail electron hydrodynamic model yields the density (n/sub 2/) and the average energy (w/sub 2/) of tail electrons and is shown to predict hot electron effects accurately.< >
A new pixel structure named base stored imager in CMOS process (BASIC), is proposed and realized with a conventional 1.5 /spl mu/m CMOS process. The BASIC cell comprises three pMOSFETs and a new photosensor, which has the gate-body tied nMOSFET structure. The BASIC cell achieves high responsivity because the photosensor amplifies the photogenerated electron-hole pairs. Dynamic range is improved by using the reset of the base through the pMOSFET and correlated double sampling operation. The structure and operation principles of the BASIC cell are presented together with measurement results from the fabricated samples. It is shown that the BASIC cell can be scaled down for large arrays and it is adequate for low voltage operation.
A new physics-based noise model of a GaAs PHEMT is developed using the characteristic potential method (CPM). The model calculates the intrinsic noise current sources using CPM. Combined with the extrinsic noise parameters extracted from the measured S-parameters, the model reproduces four noise parameters of the device accurately under low drain bias voltages without using any fitting parameters. The model is verified with a 0.2-μm GaAs PHEMT and shows excellent agreement with the measurements for all the noise parameters up to a drain voltage of 1 V Also, the proposed method allows the simulation of the microscopic noise distribution and thus allows one to obtain a physical understanding of noise mechanisms inside the device.
A new model for the impact ionization using the tail electron density is proposed. A new hydrodynamic model is used to compute the tail carrier quantities. The discretization method and numerical procedures are explained. The model parameters are extracted from the space-dependent Monte Carlo simulations. The simulated results for an n/sup +/-n/sup -/-n/sup +/ diode and a DILDD n-MOSFET are shown and give good agreement with Monte Carlo simulations and measurements, respectively.< >
Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t/sub si/ region. The reasons for the mobility decrease have been examined from a device simulation and measurements.< >
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