Sewook Hwang

Korea University

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Chulwoo Kim

Korea University

Junyoung Song

Incheon National University

Sang-Geun Bae

Korea University

Inhwa Jung

Kyung Hee University

Minyoung Song

Daegu Gyeongbuk Institute of Science and Technology

Young-Ho Kwak

Samsung (South Korea)

Hyun-Woo Lee

Korea Advanced Institute of Science and Technology

Yoonjae Choi

Korea University

Yeonho Lee

Korea University

Yeonho Lee

Korea Institute of Industrial Technology

Cooperative Institutions

Korea University

Samsung (South Korea)

SK Group (South Korea)

Seoul National University

Yonsei University

Incheon National University

Korea Advanced Institute of Science and Technology

Massachusetts Institute of Technology

Korea Research Institute of Bioscience and Biotechnology

Sungkyunkwan University

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A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process

IEEE Transactions on Circuits and Systems I Regular Papers (2013)

Young-Ho Kwak Yongtae Kim Sewook Hwang Chulwoo Kim

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm ² in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 ps _rms and the data eye opening is 0.613UI.

Line (geometry)

10.1109/tcsi.2012.2215781

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Citations (9)

An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2014)

Kyeong Min Kim Sewook Hwang Junyoung Song Chulwoo Kim

Cameras and image sensors have recently been installed in many portable devices. An image processor and a transceiver are also adopted in multimedia system-on-a-chip to handle the data from the image sensor. A wide input range and flexible data bandwidth are needed for the serial link receiver to deal with various sensor specifications. This paper presents an 11.2-Gb/s low-voltage differential signaling (LVDS) receiver for various portable devices that employ a LVDS system for data transmission between an image sensor and a processor. The designed LVDS receiver has 16 data channels and four clock channels. All the channels are selectively turned on or off, depending on the application. The proposed comparator used for the input driver of the receiver has a rail-to-rail input range and 60 mV of minimum input swing level. The clock dividing ratio and the data de-serializing factor of the proposed receiver are also programmable to deal with various color depths of image sensors. The designed LVDS receiver is fabricated in a 0.13-μm CMOS process, occupying 4-4 mm, with a 7.24-mm ² core. Power consumption is 77.38 mW, when every channel is turned on.

Transceiver

SerDes

10.1109/tvlsi.2013.2288420

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Citations (13)

A 1.62–5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques

IEEE Transactions on Circuits and Systems I Regular Papers (2017)

Sewook Hwang Junyoung Song Yeonho Lee Chulwoo Kim

We present a 1.62-5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize a simpler EQ architecture with low power dissipation. A referenceless frequency acquisition technique is also proposed. A time-to-digital converter-based pulsewidth detector supports the referenceless frequency acquisition within the range of 1.62-5.4 Gb/s. An XOR-gate-embedded charge pump and a half-rate linear phase detector were used to improve the jitter tolerance (JTOL) performance. The measured eye opening of the proposed EQ at 5.4 Gb/s was 0.68 UI with a -20-dB loss channel. The proposed receiver passed all the JTOL tests of the DisplayPort compliance specification version 1.2b. The power consumption of the receiver was 36.8 mW at 5.4 Gb/s. The receiver occupied a core area of 0.265 mm ² using 65-nm CMOS process technology.

Analog television

10.1109/tcsi.2017.2695612

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Citations (12)

A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS

1993 IEEE International Symposium on Circuits and Systems (2012)

Sewook Hwang Inhwa Jung Junyoung Song Chulwoo Kim

An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10 ^-12 at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm ² using 0.13μm CMOS process.

Adaptive equalizer

10.1109/iscas.2012.6271659

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Citations (3)

34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound

2022 IEEE International Solid- State Circuits Conference (ISSCC) (2021)

N. Sánchez Kailiang Chen Chao Chen Dan McMahill Sewook Hwang

Point-of-care ultrasound (POCUS) is transforming healthcare worldwide as a diagnostic tool with the potential to significantly reduce the delay between symptom onset and initiation of therapy. Conventional POCUS systems are based on piezoelectric transducers and cable-connected electronics, which require a costly manufacturing process and usually come with an undesirably limited channel count. Such devices typically serve a specific subset of clinical applications, as imaging at different body parts calls for different ultrasound frequencies that are beyond the bandwidth of a single piezoelectric transducer. To enable whole-body imaging, multiple probes with different frequencies, apertures and beamforming (BF) methods are generally required. This further limits the affordability and accessibility of POCUS. Recent advances in micromachined ultrasound transducers (MUTs) have offered an alternative path to addressing these challenges. However, previous attempts to integrate MUTs with chips have been incomplete, neither solving the integration problem nor achieving full ultrasound processing capabilities.

Ultrasound imaging

Point of care

10.1109/isscc42613.2021.9365808

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Citations (31)

A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- <inline-formula> <tex-math notation="TeX">$\mu\hbox{m}$</tex-math></inline-formula> CMOS Process

IEEE Transactions on Circuits & Systems II Express Briefs (2014)

Junyoung Song Sewook Hwang Hyun‐Woo Lee Chulwoo Kim

This brief proposes a 7.5-Gb/s transceiver with adaptive equalization and a bandwidth (BW)-shifting technique for ultrahigh-definition television. By applying dynamic preemphasis calibration and a BW-shifting phase-locked loop/clock and data recovery, the measured jitter of the output data with a 16.88-dB loss cable and clock are enhanced by 49.9% and 40%, respectively. In addition, a data-width-comparison-based adaptive equalizer with a self-adjusting reference voltage is proposed. With a 3.37-MHz sinusoidal jitter, the measured jitter tolerance of the proposed receiver is improved from 1.07UI to 2.97UI. The transmitter and the receiver consume 10.08 and 9.28 mW/Gb/s at 7.5 Gb/s, respectively, and occupy 0.14 and 0.15 mm ² , respectively, using a 0.13- μm complementary metal-oxide-semiconductor process.

Transceiver

10.1109/tcsii.2014.2350294

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Citations (5)

A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection

IEEE Transactions on Circuits and Systems I Regular Papers (2012)

Junyoung Song Inhwa Jung Minyoung Song Young-Ho Kwak Sewook Hwang

This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm2 and 0.94 mm2, respectively, in a 0.13 μm 1P8M CMOS process.

Transceiver

10.1109/tcsi.2012.2215779

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Citations (29)

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface

Junyoung Song Hyun-Woo Lee Soo-Bin Lim Sewook Hwang Yunsaing Kim

DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator [2]. In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance [3]. Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface [1]. However, the complexity of the transmitter and the C _IO , capacitance of I/O, increase due to additional equalizers and pre- and de-emphasis drivers. For a compact transmitter, a low-overhead boosted transmitter is developed [4]. This paper presents an adaptive-bandwidth PLL in response to the supply and channel noises, a fast pre-charged data sampler without an additional decision-feedback equalizer (DFE), a crosstalk-induced-jitter-reduction technique and a compact transmitter with pre- and de-emphasis.

Dram

SerDes

10.1109/isscc.2013.6487749

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Citations (6)

A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) (2013)

Junyoung Song Hyunwoo Lee Sewook Hwang Inhwa Jung Chulwoo Kim

A 7.5Gb/s referenceless transceiver for the ultra-high definition television is designed in a 0.13μm CMOS process. By applying the dynamic pre-emphasis calibration and the bandwidth scanning clock generators, measured eye opening and jitter of the clock are enhanced by 39.6% and 40%, respectively. Also the data-width comparison based adaptive equalizer with self-adjusting reference voltage is proposed.

Transceiver

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10.1109/aspdac.2013.6509570

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A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2016)

Junyoung Song Hyun-Woo Lee Sewook Hwang Chulwoo Kim

A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.

Dram

10.1109/tvlsi.2016.2580713

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